ASIC DFT Engineer

Location: San Jose, CA/ Toronto, Canada 

Job Type: Full Time

Summary of position:

You will be part of the IC design team, creating and bringing to market client's next generation camera processors.

Responsibilities:

  • Leadership technical position to define the overall DFT methodology for client's camera video processors
  • DFT architecture & test definition for ATPG & BIST oriented methodologies that meet automotive ISO requirements
  • Develop internal tool flows to automate test insertion, clock design & test vector development
  • Engage with external ATPG/BIST tool providers to identify the most cost effective means of meeting automotive test goals
  • Collaborate with the front end design team & implementation team to ensure successful DFT integration
  • Develop DFT specification for each roadmap ASIC
  • Engage with client¬† Quality team to ensure DFT specification will meet automotive quality goals
  • Work with the Product Engineering team to create test programs & bring up test vectors on ATE platforms
  • Manage overall ATPG test planning, coverage, test time & ATE platform specifications
  • Position will primarily address future roadmap devices but support of currently shipping products will be managed as needed

Qualifications

  • BSEE
  • 7 years of industry experience in digital design
  • Experience defining DFT methodologies for SoC type of devices
  • Experience with compression based ATPG, MBIST & LBIST methodologies
  • Experience with at speed testing of high speed SERDES interfaces
  • Fault modeling knowledge: stuck-at/transition/path delay/gate-exhaustive & IDDQ
  • Test vector planning for bring-up & production
  • Hands on ATE bring-up experience
  • Experience with Mentor, Synopsys & Cadence DFT offerings
  • Experience in RTL design with Verilog/System Verilog
  • Understanding of standard IC design methodology with simulation, synthesis, timing closure and DFT
  • Strong programming skills in C and scripting languages such as Python

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